View MAX9600_49212.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2409; Rev 1; 9/02
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators
General Description
The MAX9600/MAX9601/MAX9602 ultra-high-speed comparators feature extremely low propagation delay (500ps). These dual and quad comparators minimize propagation delay skew (10ps) and are designed for low propagation delay dispersion (30ps). These features make them ideal for applications where high-fidelity tracking of narrow pulses and low timing dispersion is critical. The differential input stage accepts a wide range of signals in the common-mode range from (VEE + 3V) to (VCC - 2V). The outputs are complementary digital signals, compatible with ECL and PECL systems, and provide sufficient current to directly drive transmission lines terminated in 50. The MAX9600/MAX9601 dual-channel ECL and dual-channel PECL output comparators incorporate latch enable (LE_, LE_), and hysteresis (HYS_). The complementary latch-enable control permits tracking, track-hold, or samplehold mode of operations. The latch enables can be driven with standard ECL logic for MAX9600 and PECL logic for MAX9601. The MAX9602 quad-channel PECL output comparator is ideal for high-density packaging in limited board space. The MAX9600/MAX9601 are available in 20-pin TSSOP packages, and the MAX9602 is offered in a 24-pin TSSOP package. The MAX9600/MAX9601/MAX9602 are specified for operation from -40C to +85C. o 500ps Propagation Delay o 30ps Propagation Delay Dispersion o 4Gbps Tracking Frequency o o o o -2.2V to +3V Input Range with +5V/-5.2V Supplies -1.2V to +4V Input Range with +6V/-4.2V Supplies Differential ECL Outputs (MAX9600) Differential PECL Outputs (MAX9601/MAX9602)
Features
MAX9600/MAX9601/MAX9602
o Latch Enable (MAX9600/MAX9601) o Adjustable Hysteresis (MAX9600/MAX9601)
Ordering Information
PART MAX9600EUP MAX9601EUP MAX9602EUG TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP 20 TSSOP 24 TSSOP
Selector Guide
PART MAX9600EUP PIN-PACKAGE 20 TSSOP SELECTION Dual ECL Output Comparator with Latch Enable and Hysteresis Dual PECL Output Comparator with Latch Enable and Hysteresis Quad PECL Output Comparator
Applications
VLSI and High-Speed Memory ATE High-Speed Instrumentation Scope/Logic Analyzer Front Ends High-Speed Triggering Threshold and Peak Detection Line Receiving/Signal Restoration
MAX9602EUG 24 TSSOP MAX9601EUP 20 TSSOP
Pin Configurations appear at end of data sheet.
Functional Diagrams
VCC VEE GND VCC VEE VCCO_ VCC VEE VCCO_
IN_+
1/2 MAX9600
Q_ ECL OUTPUT Q_ RL RL
IN_+
1/2 MAX9601
Q_ PECL OUTPUT Q_ RL RL
IN_+
1/4 MAX9602
Q_ PECL OUTPUT Q_ RL RL
IN_HYS_ RHYS_ LE_ LE_
IN_HYS_ RHYS_ LE_ LE_
IN_-
VT = -2V
VT = VCCO_ - 2V
VT = VCCO_ - 2V
THE OPEN-EMITTER OUTPUTS REQUIRE EXTERNAL PULLDOWN RESISTORS (RL). USE RESISTORS IN THE RANGE OF 50 TO 75 CONNECTED TO VT. CURRENT-CONTROLLED HYSTERESIS REQUIRES A SINGLE EXTERNAL RESISTOR (RHYS_) FROM HYS_ TO GND IN THE RANGE OF 10k TO 35k.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators MAX9600/MAX9601/MAX9602
ABSOLUTE MAXIMUM RATINGS
VS = VCC - VEE ...................................................................12.0V VCC to GND (MAX9600) .......................................................6.8V VEE to GND (MAX9600) ......................................................-6.5V Differential Input Voltage ...................................................6.5V Latch Differential Voltage ......................................................4V Common-Mode Input Voltage (VCM) .........................VEE to VCC VCCO_ to VEE (MAX9601/MAX9602)....................(VEE - 0.3V) to (VCC + 0.3V) LE_, LE_ to GND MAX9600 ....................................................(VEE - 0.3V) to 0.3V MAX9601 ..................................(VEE - 0.3V) to (VCCO_ + 0.3V) Input Current to Any Input Pin.............................................10mA HYS_ Current (MAX9600/MAX9601) ...................................-1mA Continuous Output Current .................................................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 10.9mW/oC above +70C) ........879mW 24-Pin TSSOP (derate 12.2mW/C above +70C) ........975mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), GND = 0V, RL = 50 to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER INPUT (IN_+, IN_-) Input Differential Voltage Range Input Common-Mode Voltage Input Offset Voltage Input Offset-Voltage Tempco Input Offset-Voltage Channel Matching Input Bias Current Input Bias-Current Tempco Input Offset Current Input Resistance LATCH INPUT (LE_, LE_) Latch Differential Input Voltage VLD Guaranteed by latch input current MAX9600 Latch Input Voltage Range VLR MAX9601 MAX9600 MAX9601 RHYS = RHYS = 16.4k VCCO_ 3.5V VCCO_ < 3.5V Latch Input Current HYSTERESIS INPUT (HYS_) Input-Referred Hysteresis MAX9600/MAX9601 0 30 mV ILE, ILE MAX9600 MAX9601 0.4 0.25 -2 VCCO_ - 3.5 0 5 5 2.0 3.50 0 VCCO_ VCCO_ 20 20 A V V IB TCIB IOS RIN Differential mode (VID 10mV) Common mode (VEE + 3V) VCM (VCC - 2V) VID = 5.2V VID VCM VOS TCVOS Guaranteed by input bias current tests Guaranteed by input bias current tests TA = +25C TMIN TA TMAX 8 1 6 10 0.3 10 100 5 20 -5.2 VEE + 3 1 +5.2 VCC - 2 5 9 V V mV V/C mV A nA/C A k M SYMBOL CONDITIONS MIN TYP MAX UNITS
2
_______________________________________________________________________________________
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), GND = 0V, RL = 50 to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MAX9600 TA = +25C MAX9601/MAX9602 MAX9600 Logic Output High Voltage VOH TA = TMIN MAX9601/MAX9602 MAX9600 TA = TMAX MAX9601/MAX9602 MAX9600 TA = +25C MAX9601/MAX9602 MAX9600 Logic Output Low Voltage VOL TA = TMIN MAX9601/MAX9602 MAX9600 TA = TMAX SUPPLY Positive Supply Voltage Negative Supply Voltage Supply Voltage Difference Logic Supply Voltage Positive Supply Current VCC VEE VS VCCO_ ICC Guaranteed by output swing tests Guaranteed by output swing tests VS = (VCC - VEE), guaranteed by output swing tests MAX9601/MAX9602 MAX9600 (Note 2) MAX9601 MAX9602 MAX9600 Negative Supply Current IEE (Note 2) MAX9601 MAX9602 MAX9600 Power-Supply Dissipation Common-Mode Rejection Ratio Power-Supply Rejection Ratio PDISS CMRR PSRR (Note 2) MAX9601 MAX9602 (VEE + 3V) VCM (VCC - 2V) 4.3V VCC 6.3V, -6V VEE -4V, 9.5V VS 11.5V 4.3 -6 9.5 2.4 16 19 28 21 24 38 190 220 338 70 65 5 -5.2 6.3 -4 11.5 VCC 24 27 39 28 33 49 266 307 450 dB dB mW mA mA V V V V MAX9601/MAX9602 MIN -1.10 VCCO_ - 1.10 -1.2 VCCO_ - 1.2 -1.05 VCCO_ - 1.05 -1.95 VCCO_ - 1.95 -2.0 VCCO_ - 2.0 -1.9 VCCO_ - 1.9 TYP -0.94 VCCO_ - 0.94 -1.02 VCCO_ - 1.02 -0.87 VCCO_ - 0.87 -1.72 VCCO_ - 1.72 -1.78 VCCO_ - 1.78 -1.66 VCCO_ - 1.66 MAX -0.75 VCCO_ - 0.75 -0.8 VCCO_ - 0.8 -0.70 VCCO_ - 0.70 -1.55 VCCO_ - 1.55 -1.6 VCCO_ - 1.6 -1.50 VCCO_ - 1.5 V V UNITS
MAX9600/MAX9601/MAX9602
_ OUTPUT (Q_, Q_)
_______________________________________________________________________________________
3
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators MAX9600/MAX9601/MAX9602
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS_ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL = 5pF, GND = 0V, RL = 50 to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Tracking Frequency Toggle Rate Minimum Pulse Width Propagation Delay Propagation Delay Tempco Propagation Delay Skew Propagation Delay Match Propagation Delay Dispersion Overdrive Propagation Delay Dispersion Common-Mode Voltage Propagation Delay Dispersion Input Slew Rate Propagation Delay Dispersion Duty Cycle Propagation Delay Dispersion Pulse Width Unit-to-Unit Propagation Delay Match Output Jitter Input Capacitance Latch Setup Time Latch Hold Time Minimum Pulse Width Latch to Output Delay Rise Time and Fall Time CIN tLS tLH tLPW tLPD tR, tF VIN = 1VP-P input overdrive = 100mV SYMBOL fMAX tPW TCtPD tPDSKEW Input overdrive = 100mV (Note 4) Input overdrive = 100mV (Note 5) 10mV to 100mV 100mV to 2V (VEE + 3V) VCM (VCC - 2V) 0.2V/ns to 10V/ns 10% to 90% at 250MHz 350ps to 1ns Input overdrive = 100mV VIN = 2VP-P; 50MHz IN_+ or IN_, with respect to GND Figure 1, (Notes 3, 6) Figure 1, (Notes 3, 6) Figure 1 Figure 1 20% to 80%, Figure 1 250 300 CONDITIONS VOUT = 550mVP-P, input overdrive = 100mV VOUT = 550mVP-P, input overdrive = 100mV MIN TYP 4 250 500 0.5 10 40 15 40 10 40 ps 30 20 50 300 2 80 85 250 200 200 ps fs pF ps ps ps ps ps 700 MAX UNITS Gbps ps ps ps/C ps ps ps
tPD-, tPD+ Input overdrive = 100mV, Figure 1, (Note 3)
All devices are 100% production tested at TA = +25C. Specifications over temperature are guaranteed by design. Does not include output state current in Q_, Q_. Guaranteed by design. Propagation delay skew (tPDSKEW) is for a single channel and is the difference between the propagation delay to the highto-low output transition vs. the low-to-high output transition. Note 5: Propagation delay match is the difference of tPD- or tPD+ of one channel to the tPD- or tPD+ of another channel of the same device. Note 6: Latch setup and hold-timing specifications are for a differentially driven latch signal. Note 1: Note 2: Note 3: Note 4:
4
_______________________________________________________________________________________
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators
Typical Operating Characteristics
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL = 5pF, GND = 0V, RL = 50 to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%, TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
PROPAGATION DELAY vs. INPUT OVERDRIVE (VCC = 10mV TO 100mV)
MAX9600/1/2 toc01
PROPAGATION DELAY vs. INPUT OVERDRIVE (VOD = 0.1V TO 2V)
540 PROPAGATION DELAY (ps) 520 500 480 460 440 420 400
MAX9600/1/2 toc02
PROPAGATION DELAY vs. SOURCE IMPEDANCE
MAX9600/1/2 toc03
530 520 PROPAGATION DELAY (ps) 510 500 490 480 470 10 20 30 40 50 60 70 80
560
3500 3000 PROPAGATION DELAY (ps) 2500 2000 1500 1000 500 0
90 100
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 INPUT OVERDRIVE (V)
0
100
200
300
400
500
600
INPUT OVERDRIVE (mV)
SOURCE IMPEDANCE ()
PROPAGATION DELAY vs. CAPACITIVE LOAD
MAX9600/1/2 toc04
PROPAGATION DELAY vs. TEMPERATURE
MAX9600/1/2 toc05
PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9600/1/2 toc05
1500 1250 PROPAGATION DELAY (ps) 1000 750 500 250 0 0 5 10 15 20 25
550 540 PROPAGATION DELAY (ps) 530 520 510 500 490 480 470
530 520 PROPAGATION DELAY (ps) 510 500 490 480 470
30
-50
-25
0
25
50
75
100
-3
-2
-1
0
1
2
3
CAPACITIVE LOAD (pF)
TEMPERATURE (C)
COMMON-MODE VOLTAGE (V)
_______________________________________________________________________________________
5
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators MAX9600/MAX9601/MAX9602
Typical Operating Characteristics (continued)
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL = 5pF, GND = 0V, RL = 50 to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%, TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
PROPAGATION DELAY vs. PULSE WIDTH
MAX9600/1/2 toc07
PROPAGATION DELAY vs. INPUT SLEW RATE
MAX9600/1/2 toc08
PROPAGATION DELAY vs. DUTY CYCLE
540 PROPAGATION DELAY (ps) 530 520 510 500 490 480 470 460 FREQUENCY = 250MHz
MAX9600/1/2 toc09
550 540 PROPAGATION DELAY (ps) 530 520 510 500 490 480 470 460 450 300 400 500 600 700 800 900
540 530 PROPAGATION DELAY (ps) 520 510 500 490 480 470
550
450 0 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) INPUT SLEW RATE (V/ns)
1000
PULSE WIDTH (ps)
INPUT OFFSET VOLTAGE vs. TEMPERATURE
MAX9600/1/2 toc10
HYSTERESIS vs. RHYS TO GND
MAX9600/1/2 toc11
HYSTERESIS vs. TEMPERATURE
34 33 HYSTERESIS (mV) 32 31 30 29 28 27 RHYS = 16.4k
MAX9600/1/2 toc12
300 200 100 0 -100 -200 -300 -50 -25 0 25 50 75
70 60 HYSTERESIS (mV) 50 40 30 20 10 0
35
INPUT OFFSET VOLTAGE (V)
26 25 10 15 20 25 RHYS (k) 30 35 40 -50 -25 0 25 50 75 100 TEMPERATURE (C)
100
TEMPERATURE (C)
6
_______________________________________________________________________________________
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators
Typical Operating Characteristics (continued)
(VCC = 5V, VEE = -5.2V, VCM = 0V, HYS _ = open (MAX9600/MAX9601), LE_ = low, LE_ = high (MAX9600/MAX9601), CL = 5pF, GND = 0V, RL = 50 to -2V (MAX9600), VCCO_ = 5V, RL = 50 to 3V (MAX9601/MAX9602), input slew rate = 2V/ns, duty cycle = 50%, TA = TMIN to TMAX. Typical values are at TA = +25C, unless otherwise noted.) (Note 1)
MAX9600/MAX9601/MAX9602
INPUT BIAS CURRENT vs. TEMPERATURE
MAX9600/1/2 toc13
INPUT BIAS CURRENT vs. INPUT VOLTAGE DIFFERENTIAL
MAX9600/1/2 toc14
OUTPUT VOLTAGE HIGH vs. TEMPERATURE
MAX9600/1/2 toc15
8.0 7.5 INPUT BIAS CURRENT (A) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 -50 -25 0 25 50 75
20 TA = +85C INPUT BIAS CURRENT (A) 15
-0.75 -0.80 OUTPUT VOLTAGE HIGH (V) RL = 200 -0.85 RL = 100 -0.90 -0.95 -1.00 RL = 50
10
TA = +25C
5
0 TA = -40C -5 100 -6 -4 -2 0 2 4 6 TEMPERATURE (C) INPUT VOLTAGE DIFFERENTIAL (V)
-1.05 -50 -25 0 25 50 75 100 TEMPERATURE (C)
OUTPUT VOLTAGE LOW vs. TEMPERATURE
MAX9600/1/2 toc16
OUTPUT RESPONSE TO 100MHz INPUT
MAX9600/1/2 toc17
OUTPUT RESPONSE TO 4Gbps INPUT
MAX9600/1/2 toc18
-1.55
OUTPUT VOLTAGE LOW (V)
-1.60
RL = 100 RL = 200
VIN 50mV/div
VIN 50mV/div
-1.65
-1.70 RL = 50 -1.75 QOUT 200mV/div
QOUT - QOUT 200mV/div
-1.80 -50 -25 0 25 50 75 100 2ns/div 200ps/div TEMPERATURE (C)
_______________________________________________________________________________________
7
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators MAX9600/MAX9601/MAX9602
Timing Diagram
LATCH LE_ VLD LE_ VLR (MIN) tLPW tLPD tFW(MIN) IN_VID IN_+ tPDtPD+ VCM tLS tLH VLE + VLE 2 COMPARE LATCH VLR (MAX)
Q_ 80% VOH - VOL Q_ VOH + VOL 2 20% tR tF 20% 80%
Figure 1. MAX9600/MAX9601/MAX9602 Timing Diagram
Pin Descriptions
MAX9600/MAX9601
PIN MAX9600 1 2 3 -- 4 5 6, 15 7, 14 8 9 10 11 12 13 16 17 18 -- 19 20 MAX9601 1 2 -- 3 4 5 6, 15 7, 14 8 9 10 11 12 13 16 17 -- 18 19 20 NAME QA QA GND VCCOA LEA LEA VEE VCC HYSA INAINA+ INB+ INBHYSB LEB LEB GND VCCOB QB QB Channel A Output Channel A Complementary Output Channel A Output Ground Channel A Output Driver Positive Supply Channel A Latch-Enable Input Channel A Latch-Enable Complementary Input Negative Supply Voltage Positive Supply Voltage Channel A Hysteresis Input Channel A Minus Input Channel A Plus Input Channel B Plus Input Channel B Minus Input Channel B Hysteresis Input Channel B Latch-Enable Complementary Input Channel B Latch-Enable Input Channel B Output Ground Channel B Output Driver Positive Supply Channel B Complementary Output Channel B Output FUNCTION
8
_______________________________________________________________________________________
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators
Pin Descriptions (continued)
MAX9602
PIN 1 2 3, 9 4 5 6, 12 7 8 10 11 13 14 15 16 17 18 19 20 21 22 23 24 NAME INA+ INAVEE INB+ INBVCC INC+ INCIND+ INDQD QD VCCOD QC QC VCCOC QB QB VCCOB QA QA VCCOA Channel A Plus Input Channel A Minus Input Negative Supply Voltage Channel B Plus Input Channel B Minus Input Positive Supply Voltage Channel C Plus Input Channel C Minus Input Channel D Plus Input Channel D Minus Input Channel D Complementary Output Channel D Output Channel D Output Driver Positive Supply Channel C Complementary Output Channel C Output Channel C Output Driver Positive Supply Channel B Complementary Output Channel B Output Channel B Output Driver Positive Supply Channel A Complementary Output Channel A Output Channel A Output Driver Positive Supply FUNCTION
MAX9600/MAX9601/MAX9602
Detailed Description
The MAX9600/MAX9601/MAX9602 ultra-high-speed comparators feature extremely low propagation delay (500ps). These dual and quad comparators minimize channel-to-channel skew (10ps) and are designed for low propagation delay dispersion. These features make them ideal for applications where high-fidelity tracking of narrow pulses and low timing dispersion is critical. The devices operate from either standard supply levels of -5.2V/+5V or shifted levels of -4.2V/+6V. The differential input stage accepts a wide range of signals in the common-mode range from (VEE + 3V) to (VCC - 2V) with a CMRR of 70dB (typ). The outputs are complementary digital signals, compatible with ECL and PECL systems, and provide sufficient current to directly drive transmission lines terminated in 50. The ultra-fast operation makes signal processing possible at a data rate up to 4Gbps. Figure 2 shows a 1Gbps (500MHz) example with an input-signal level of 100mVP-P.
INPUT 50mV/div
0V
-0.9V OUTPUT 200mV/div -1.7V
500ps/div
Figure 2. Signal Processed at 500MHz with Input-Signal Level of 100mVRMS.
_______________________________________________________________________________________
9
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators MAX9600/MAX9601/MAX9602
The MAX9600/MAX9601 incorporate latch-enable and hysteresis control. Hysteresis rejects noise and prevents oscillations on low-slew input signals. The latchenable control permits tracking or sampling mode of operations. Drive the complementary latch enable with standard ECL logic for MAX9600 and PECL logic for MAX9601. The MAX9602 quad-channel PECL output comparator does not include the latch-enable or hysteresis control functions. output voltage of 2.5V at HYS_ divided by the desired hysteresis current level in the range of 0 to 200A. RHYS of 10k to 35k resistors provides hysteresis of 60mV to 5mV (see the Hysteresis vs. R HYS to GND graph in the Typical Operating Characteristics section). For a zero hysteresis (0A hysteresis current), leave HYS_ open or connect it to VCC.
Propagation Delay Dispersion
Propagation delay dispersion is defined as a variation in propagation delay as a function of change in input conditions. In an automatic test system pin-driver electronics, for example, the dispersion determines the maximum edge resolution. Many factors can affect the dispersion, such as commonmode voltage, overdrive, input slew rate, duty cycle, and pulse width. The typical propagation delay dispersions of the MAX9600/MAX9601/MAX9602 are less than 10ps to 40ps (see the Typical Operating Characteristics and Electrical Characteristics sections).
Applications Information
Layout
Special layout precautions exist due to the large gainbandwidth characteristic of the MAX9600/MAX9601/ MAX9602. Use a printed circuit board with a good, lowinductance ground plane. Mount 0.01F ceramic decoupling capacitors as close to the power-supply inputs as possible. Minimize lead lengths on the inputs and outputs to avoid unwanted parasitic feedback around the comparators. Use surface-mount chip components to minimize lead inductance. Pay close attention to the bandwidth of the decoupling and terminating components. Use microstrip layout and terminations at the input and output. Avoid discontinuities in differential impedance. Maximize common-mode noise immunity by maintaining the distance between differential traces and avoid sharp corners. Minimize the number of vias to prevent impedance discontinuities. Match the electrical length of the traces to minimize skew.
Comparators with Latch Enable (MAX9600/MAX9601)
The latch-enable function allows the comparator to be used in a sampling mode. When LE_ is low (LE_ is high), the comparator tracks the input signal. When LE_ is driven high (LE_ is low), the outputs are forced to an unambiguous logic state, dependent on the input conditions at the time of the latch input transition. If the latch-enable function is not used, connect the appropriate LE_ input to a low ECL/PECL logic, and its complementary LE_ input to a high ECL/PECL logic level (see Table 1). The input range of the MAX9600 differential latchenable inputs is 400mV to 2V. The logic-input swing excursion must fall within an input-voltage range (VLR) of -2V to 0 to work properly. The input range of the MAX9601 differential latch-enable inputs is 250mV to 3.5V. The logic-input swing excursion must fall within an input-voltage range (VLR) of 0 to 3.5V for (VCCO_ < 3.5V) or VLR of (VCCO_ - 3.5V) to VCCO_ for (VCCO_ 3.5V) to work properly.
Input Slew-Rate Requirements
As with all high-speed comparators, the high gainbandwidth product of these devices can create oscillation problems when the input goes through the threshold region. This is typically due to parasitic paths, which cause positive feedback to occur. For clean switching without oscillation or steps in the output waveform for the MAX9600/MAX9601, use an input with a slew rate of 5V/s or faster. For the MAX9602, use a slew rate of 25V/s or faster. The tendency of the part to oscillate is a function of the layout and source impedance of the circuit employed. Poor layout and larger source impedance increases the minimum slew-rate requirement. Adding hysteresis accommodates slower inputs (see the Hysteresis section). Hysteresis (MAX9600/MAX9601) Hysteresis can be introduced to prevent oscillation or multiple transitions due to noise. The MAX9600/ MAX9601 feature current-controlled hysteresis, which is set by placing a resistor between HYS_ and GND. The value of the current-setting resistor is determined by the
10
Table 1. Latch-Enable Truth Table
LATCH-ENABLE INPUT LE_ 0 1 0 1
_ LE_
1 0 0 1
OPERATION Compare Mode. Output follows input state. Latch Mode. Output latches to last known output state. Invalid condition, output is in unknown state.
______________________________________________________________________________________
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators
Timing Information (MAX9600/MAX9601)
The timing diagram (Figure 1) illustrates the operation of a comparator with latch enable. The top line of the diagram illustrates a latch-enable pulse. Initially, the latch-enable input (LE, LE_) is differentially high, which places the comparator in latch mode. When the input signal (IN_+, IN_-) switches from low to high, the output (Q_, Q_) remains latched to the previous low state. When the latch-enable input goes differentially low, starting the compare function, the output responds to the input and transitions to high after a time (tLPD). The leading edges of the subsequent input signal switch the comparator after time interval tPD+ or tPD- (depending on the direction of the input transitions) until a high latch-enable pulse places the device in latch mode again. The input signal must occur at minimum time (tLS) before the latch rising edge, and must maintain its state for at least tLH after the rising edge. A minimum latch-pulse width (tLPW) of 250ps (typ) is needed for proper latch operation.
ECL/PCL
The MAX9600/MAX9601/MAX9602 outputs are emitter followers that require external resistive connections to a voltage source (VT) more negative than the lowest VOL for proper static and dynamic operation. When properly terminated, the outputs provide appropriate levels, VOL or V OH , for ECL (MAX9600) or PECL (MAX9601/ MAX9602). Output-current polarity always sinks into the termination scheme during proper operation. ECL-output signal levels are referenced to GND, and PECL-output signals are referenced to VCCO_.
MAX9600/MAX9601/MAX9602
Chip Information
MAX9600 TRANSISTOR COUNT: 558 MAX9601 TRANSISTOR COUNT: 600 MAX9602 TRANSISTOR COUNT: 608 PROCESS: Bipolar
Pin Configurations
TOP VIEW
QA 1 QA 2 GND 3 LEA 4 LEA 5 VEE 6 VCC 7 HYSA 8 INA- 9 INA+ 10 20 QB 19 QB 18 GND 17 LEB QA 1 QA 2 VCCOA 3 LEA 4 LEA 5 VEE 6 VCC 7 HYSA 8 INA- 9 INA+ 10 20 QB 19 QB 18 VCCOB 17 LEB INA+ 1 INA- 2 VEE 3 INB+ 4 INB- 5 VCC 6 INC+ 7 INC- 8 VEE 9 IND+ 10 IND- 11 24 VCCOA 23 QA 22 QA 21 VCCOB
MAX9600
16 LEB 15 VEE 14 VCC 13 HYSB 12 INB11 INB+
MAX9601
16 LEB 15 VEE 14 VCC 13 HYSB 12 INB11 INB+
MAX9602
20 QB 19 QB 18 VCCOC 17 QC 16 QC 15 VCCOD 14 QD 13 QD
TSSOP-20
TSSOP-20
VCC 12
TSSOP-24
______________________________________________________________________________________
11
Dual ECL and Dual/Quad PECL, 500ps, Ultra-High-Speed Comparators MAX9600/MAX9601/MAX9602
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
TSSOP4.40mm.EPS

▲Up To Search▲

Price & Availability of MAX9600

	To Download MAX9600 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .